Here's a historical view of the Power chip family, moving from the Power1 implemented in IBM's 1 micrometer chip baking processes up to the Power7 implemented in 45 nanometer processes:
This is the latest-greatest public roadmap for the Power chips, which as you can see is a little short on details for Power8 and which doesn't even mention the plus versions of the chips:
The following AIX roadmap is interesting in that it shows IBM's Unix variant being tweaked to exploit the Power7+ chips sometime in the second half of 2011.
To see where IBM might be taking the Power7+ and Power8 chips, it makes sense to look at how the chips and memory components have evolved over time. Here's how the latest several generations of Power chips have stacked up:
POWER7 was released in February 2010 and was a substantial evolution from the POWER6 design, focusing more on power efficiency through multiple cores and simultaneous multithreading.
While the POWER6 features a dual-core processor, each capable of two-way simultaneous multithreading (SMT), the IBM POWER7 processor has eight cores, and four threads per core, for a total capacity of 32 simultaneous threads. Its power consumption is similar to the preceding POWER6, while quadrupling the number of cores, with each core having higher performance.
POWER7
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Produced 2010
Designed by IBM
Max. CPU clock rate 2.4 GHz to 4.25 GHz
Min. feature size 45 nm
Instruction set Power Architecture
Microarchitecture Power ISA v.2.06
Cores 4, 6, 8
L1 cache 32+32 KB/core
L2 cache 256 KB/core
L3 cache 32 MB
As of July 2011, the range of POWER7 systems includes "Express" models (710, 720, 730, 740 and 750), Enterprise models (770, 780 and 795) and High Performance computing models (755 and 775). Enterprise models differ in having Capacity on Demand capabilities. Maximum specifications are shown in the table below.
IBM POWER7 servers | |||
Name | Number of chips | Number of cores | CPU clock frequency |
710 Express | 1 | 6 | 3.7 GHz |
710 Express | 1 | 8 | 3.55 GHz |
720 Express | 1 | 8 | 3.0 GHz |
730 Express | 2 | 12 | 3.7 GHz |
730 Express | 2 | 16 | 3.55 GHz |
740 Express | 2 | 12 | 3.7 GHz |
740 Express | 2 | 16 | 3.55 GHz |
750 Express | 4 | 24 | 3.72 GHz |
750 Express | 4 | 32 | 3.22 GHz or 3.61 GHz |
755 | 4 | 32 | 3.61 GHz |
770 | 8 | 48 | 3.5 GHz |
770 | 8 | 64 | 3.1 GHz |
775 (Per Node) | 32 | 256 | 3.83 GHz |
780 (MaxCore mode) | 8 | 64 | 3.86 GHz |
780 (TurboCore mode) | 8 | 32 | 4.14 GHz |
795 | 32 | 192 | 3.7 GHz |
795 (MaxCore mode) | 32 | 256 | 4.0 GHz |
795 (TurboCore mode) | 32 | 128 | 4.25 GHz |
POWER6 :
POWER6 was announced on May 21, 2007. It adds VMX to the POWER series. It also introduces the second generation of IBM ViVA, ViVA-2. It is a dual-core design, reaching 5.0 GHz at 65 nm. It has very advanced interchip communication technology. Its power consumption is nearly the same as the preceding POWER5, whilst offering doubled performance.
As of 2008, the range of POWER6 systems includes "Express" models (the 520, 550 and 560) and Enterprise models (the 570 and 595). The various system models are designed to serve any sized business. For example, the 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi-environment data centers. The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-pluggable processor and memory "books". All Power systems are noted for their excellent scalability and storage capabilities.
IBM POWER6 servers | |||
Name | Number of sockets | Number of cores | CPU clock frequency |
520 Express | 2 | 4 | 4.2 GHz or 4.7 GHz |
550 Express | 4 | 8 | 4.2 GHz or 5.0 GHz |
560 Express | 8 | 16 | 3.6 GHz |
570 | 8 | 16 | 4.4 GHz or 5.0 GHz |
570 | 16 | 32 | 4.2 GHz |
575 | 16 | 32 | 4.7 GHz |
595 | 32 | 64 | 4.2 GHz or 5.0 GHz |
POWER6
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========
Produced 2007
Designed by IBM
Min. feature size 65 nmDesigned by IBM
Instruction set Power Architecture
Microarchitecture Power ISA v.2.05
Cores 2
L1 cache 64+64 KB/core
L2 cache 4 MB/core
L3 cache 32 MB/chip (off-chip)
POWER5
POWER5 MCM with four processors and four 36 MB external L3 cache modules.
IBM introduced the POWER5 processor in 2004. It is a dual-core processor with support for simultaneous multithreading with two threads, so it implements 4 logical processors. Using the Virtual Vector Architecture, several POWER5 processors can act together as a single vector processor. The POWER5 added more instructions to the ISA.
The POWER5+ added even more instructions, bringing the ISA to version 2.02.
Key enhancements introduced into the POWER5 processor and system design points include:
- Designed for entry and high-end servers
- Simultaneous multi-threading
- Dynamic resource balancing to efficiently allocate system resources to each thread
- Software-controlled thread prioritization
- Dynamic power management to reduce power consumption without affecting performance
- Micro-Partitioning technology (hardware support for Shared Processor Partitions)
- Virtual storage, virtual Ethernet
- Enhanced scalability, parallelism
- Enhanced memory subsystem
- Improved performance
- Compatibility with existing POWER4 systems
- Enhanced reliability, availability, serviceability
POWER4 design | POWER5 design | |
L1 data cache | 2-way set associative FIFO a | 4-way set associative LRU b |
L2 cache | 8-way set associative 1.44 MB | 10-way set associative 1.9 MB |
L3 cache | 32 MB (118 clock cycles) | 36 MB (~80 clock cycles) |
Memory bandwidth | 4 GB/second per chip | ~16 GB/second per chip |
Simultaneous multi-threading | No | Yes |
Processor addressing | 1 processor | 1/10th of processor |
Dynamic power management | No | Yes |
Size | 412 mm 2 | 389 mm 2 |
